SPI register map

Register Name	Register offset	Field name	Field position	Description
CONTROL REGISTER	0x0	spi_mode	0	DEPRECATED
		divider_setting	3:1	Clock prescaler setting
		spi_transfer_length	7:4	SPI transfer length
		clockgen_enable	8	Enable SCLK generator
		spi_direction	9	Set transfer direction (MSB/LSB first)
		start_generator_enable	12	Enables automatic periodic transfer
		ss_polarity	13	slave select signal polarity
		ss_deassert_delay_enable	14	When 1 the SS_DELAY delay is applied at both start and end of a transaction
		transfer_length_choice	15	Toggle internal/external transfer length selection
		latching_edge	16	Select data latching edge (raising or falling)
		clock_polarity	17	Select polarity of the clock
SS_DELAY	0x4	spi_delay	31:0	Delay between slave select assertion and transfer start
SPI_DATA_OUT[0]	0x8	data	31:0	Channel 0 data to transmit
TRANSFER START	0xC	start	31:0	A write to this register starts a spi transaction
SPI_DATA_IN[0]	0x10	data	31:0	Channel 0 received data
SCLK_PERIOD	0x14	period	31:0	Period (in number of main clock cycles) of the SPI clock signal
SPI_DATA_OUT[1]	0x18	data	31:0	Channel 1 data to transmit
SPI_DATA_OUT[2]	0x1C	data	31:0	Channel 2 data to transmit
SPI_DATA_IN[1]	0x20	data	31:0	Channel 1 received data
SPI_DATA_IN[2]	0x24	data	31:0	Channel 2 received data