Communication peripherals¶
I2C¶
This module implements a standard I2C master interface. Since the main design goal is configuration and control of external integrated circuits, the implementation is not complete and only few features listed below have been worked on.
100 kbit/s standard mode only
Master role only
7 bit addressing only
Write support only
The fundamental operation of the core is the register write operation, a 2 bytes write operation where the first byte represents the register address and the second one the value to be set.
The internal structure of the module is shown in the image above. The control unit block is responsible for the Simplebus interface only, it consists of a state machine that accepts commands over that interface and then outputs the appropriate signals needed for the selected operation. Once a transfer is requested, the transfer controller takes over, this block, also containing a FSM, is at the core of the module operations, and it is responsible for the control of which data should go on the wire. It is also in charge of ensuring timing compliance with the standard controlling the spacing between transmissions. Lastly the data engine shifts the out of the core onto the SDA line when needed. The timebase signals is generated by the core of the Enable Generator module, depending on the usage needs the timebase frequency can be either fixed and determined by a parameter or modifiable at runtime.
PARAMETERS
FIXED_PERIOD:Enables fixed period mode. Default value “FALSE”
FIXED_PERIOD_WIDTH: This parameter controls the SCL frequency when fixed period mode is enabled. Default value 1000
SCL_TIMEBASE_DELAY: This parameter controls the amount of delay in clock cycles between the timebase edge and the output SCL edge 15
INPUTS
clock: Main clock input
reset: Active low synchronous reset input
i2c_scl_in: I2C SCL input, used in conjunction with an external tristate IO buffer
i2c_sda_in: I2C SDA input, used in conjunction with an external tristate IO buffer
OUTPUTS
i2c_scl_out: I2C SCL output, used in conjunction with an external tristate IO buffer
i2c_scl_out_en: I2C SCL output eable, used to control an external tristate IO buffer
i2c_sda_out: I2C SDA output, used in conjunction with an external tristate IO buffer
i2c_sda_out_en: I2C SDA output eable, used to control an external tristate IO buffer
INTERFACES
sb: Simplebus slave interface for control and configuration
Known compatible parts
-Silicon labs Si5351 clock generator IC
SPI¶
This module implements a Multichannel SPI master peripheral. The main configuration and control is done through the Simplebus Interface, however once configured the data transfers can also be fully controlled through the external AXI stream interface
The operations of this module are controlled by the Control Unit. This submodule interfaces to the outside world through the Simplebus Interface and controls all other aspects of the core. This also listens on the AXI steam interface and starts transfers as necessary. As in all SPI interfaces the design revolves around a parallel to serial shift register (SPI register here). This is directly controlled by the Transfer engine, who controls the transmission length, the timing and polarity of slave select signals, the endianness of transferred data etc. An internal enable generator allows totally standalone periodic transfers operations. An internal prescaler derives the SCLK signal from the main clock input.
PARAMETERS
BASE_ADDRESS: Base address for the Simplebus interface. Default value 0x43C00000
SS_POLARITY_DEFAULT: State of the Slave select signals upon reset. Default value 0
N_CHANNELS: Number of SPI channels supported by this peripheral. Default value 3
OUTPUT_WIDTH: Width of the output data AXI stream. Default value 32
INPUTS
clock: Main clock input
reset: Active low synchronous reset input
external_transfer_length: Length of the SPI transfer when externally triggered
MISO: SPI Master Input Slave Output signal
SPI_write_valid: AXI stream slave transfer control interface valid signal
SPI_write_data: AXI stream slave transfer control interface data signal
OUTPUTS
data_valid: Received data AXI stream master valid signal
data_out: Received data AXI stream master data signal
MOSI: SPI Master Output Slave Input signal
SCLK: SPI Slave Clock signal
SS: SPI slave select signal.
SPI_write_ready: AXI stream slave transfer control interface ready signal
INTERFACES
sb: Simplebus slave interface for control and configuration
Known compatible parts
Analog Devices AD2S1210 Resolver to digital converter
Analog Devices LTC2313 Analog to digital converter
RTCU¶
The RTCU family of modules implement a real time communication protocol specifically designed to meet the needs of the power electronics community. Being still under heavy development documentation is provided at this stage.